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121. If the inputs to the diagram shown in figure «2» of the illustration were A=0 and B=0, what logic levels would be indicated at points «C», «D», «E», and «F» respectively
With A=0 and B=0, the NAND gate outputs 1, the NOR gate outputs 1, the inverter outputs 0, and the final OR gate outputs 1, resulting in C=1, D=1, E=0, and F=1.
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