Full access allows:
- Solve all tests online without limits;
- Remove all advertisements on website;
- Adding questions to favorite list;
- Save learning progress;
- Save results of practice exams;
- Watching all wrong answered questions.
55. In the circuit shown in Fig. 8A4, U5 pins 1 and 4 are high and both are in the reset state. Assume one clock cycle occurs of Clk A followed by one cycle of Clk B. What are the output states of the two D-type flip flops?
Both flip-flop outputs are high; pin 5 is high and pin 9 is high.
Comments (0)
There are no comments at the moment. If you found an error or think question is incorrect, tell everyone about it
Only signed in users can write comments
Signin